The present invention relates to a semiconductor device and manufacturing method thereof. More specifically, the present invention relates to a semiconductor device having a capacitor and a contact plug in a DRAM (Dynamic Random Access Memory) or the like, and to a manufacturing method thereof. The present invention also relates to MIM capacitor fabrication methods and systems.
A semiconductor memory, such as a DRAM, mainly consists of a transistor and a capacitor. Therefore, improvement in the efficiency of these two structures tends to be the direction in which technology is developing. DRAM is a volatile memory, and the way to store digital signals is decided by charge or discharge of the capacitor in the DRAM. When the power applied on the DRAM is turned off, the data stored in the memory cell completely disappears. A typical DRAM cell usually includes at least one field effect transistor (FET) and one capacitor. The capacitor is used to store the signals in the cell of DRAM. If more charges can be stored in the capacitor, the capacitor has less interference when the amplifier senses the data. In recent years, the memory cell of a DRAM has been miniaturized more and more from generation to generation. Even if the memory cell is minimized, a specific charge is essentially stored in the storage capacitor of the cell to store the information.
When the semiconductor enters the deep sub-micron process, the size of the device becomes smaller. For the conventional DRAM structure, this means that the space used by the capacitor becomes smaller. Since computer software is gradually becoming huge, even more memory capacity is required. In the case where it is necessary to have a smaller size with an increased capacity, the conventional method of fabricating the DRAM capacitor needs to change in order to fulfill the requirements of the trend.
There are two approaches at present for reducing the size of the capacitor while increasing its memory capacity. One way is to select a high-dielectric material, and the other is to increase the surface area of the capacitor.
There are two main types of capacitor that increase capacitor area. These are the deep trench-type and the stacked-type, where digging out a trench and filling the trench with a conductive layer, a capacitive dielectric layer and a conductive layer in sequence for the capacitor form the deep trench-type capacitor.
When a dielectric material with a relatively high dielectric constant is used in a stacked capacitor, the materials for manufacturing the upper and the bottom electrodes need to be gradually replaced in order to enhance the performance of the capacitor. A structure known as a metal-insulator-metal (MIM) structure possesses a low-interfacial reaction specificity to enhance the performance of the capacitor. Therefore, it has become an important topic of research for the semiconductor capacitor in the future.
Cell areas are reduced, as a semiconductor device needs ultra-high integrity. Thus, many studies for increasing the capacitance of a capacitor are being developed. There are various ways of increasing the capacitance such as forming a stacked or trench typed three-dimensional structure, whereby a surface area of a dielectric layer is increased.
In order to constitute a cell area in a DRAM fabrication, transistors and the like are formed on a semiconductor substrate, storage and plate electrodes of polycrystalline silicon and a dielectric layer are formed wherein the dielectric layer lies between the electrodes, and metal wires are formed to connect the devices one another.
The obtainable capacitance of the storage capacitor tends to decrease dependent upon the level of the miniaturization of the storage cell. On the other hand, the necessary capacitance of the capacitor is almost constant when the storing voltage to be applied across the capacitor is fixed. Therefore, it is necessary for the capacitor to compensate the capacitance decrease due to the miniaturization by, for example, increasing the surface area of the capacitor. This surface area increase has been popularly realized by increasing the thickness of the lower electrode (or, storage electrode) of the capacitor. A typical capacitor utilized in DRAM fabrication is the Metal Insulator Metal (MIM) capacitor, which is usually located in the memory region of DRAM and embedded DRAM to increase the capacitance of the capacitor.
In the conventional method of fabricating a semiconductor device, a polysilicon material is usually to be taken for the electrodes of the capacitors. In this case, the higher the temperature is used in the process of annealing on the dielectric thin film, the lesser the defect exists in the dielectric thin film.
In conventional embedded DRAM fabrication processes, a Co-salicide gate is generally utilized in association with logic circuits. The term xe2x80x9cSalicidexe2x80x9d generally refers to xe2x80x9cself-aligned silicidexe2x80x9d and is well known in the art of DRAM semiconductor fabrication. It is difficult to apply Co-salicide gate for use in memory cells. The root cause of this difficulty lies in the fact that in order to utilize a Co-salicide gate efficiently, it is necessary to possess enough of a gate to contact extension for window process, which resulted in the ability of the cell size to shrink efficiently. Although SAC (self-aligned contact) is generally better to utilize for gate resistance performance and is more compatible with logical processes, the SAC process is difficult to use in reducing cell size and continues to present drawbacks.
Thus, the present inventor has concluded that a need exists for a new process, which combines the salicide gate, and SAC process in the memory cell area without the need for extra mask and trading-off circuit performance.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore one aspect of the present invention to provide an improved semiconductor fabrication method and system.
It is another aspect of the present invention to provide a method and system for fabricating a MIM capacitor.
It is yet another aspect of the present invention to provide a method and system for fabricating a MIM capacitor utilized in a DRAM-based semiconductor device.
It is yet another aspect of the present invention to combine a salicide gate and SAC (self-aligned contact) techniques in a memory cell without requiring an additional photo mask and trade-offs in circuit performance thereof.
The above and other aspects of the present invention are achieved as is now described. A method and system for fabricating a capacitor utilized in a semiconductor device. A salicide gate is designated for use with the semiconductor device. A self-aligned contact (SAC) may also be configured for use with the semiconductor device. The salicide gate and the self-aligned contact are generally in a memory cell area of the semiconductor device to thereby permit the efficient shrinkage of memory cell size without an additional mask or weakening of associated circuit performance. Combining, the self-aligned contact and the salicide gate in the same memory cell area can effectively reduce gate resistance.